1. Field of the Invention
The present invention relates to an IC memory card incorporating an address decoding function.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional IC memory card which is described in "IC MEMORY CARD GUIDELINE" issued in, Sept. 1986 by the Personal Computer Business Committee of the Japan Electronic Industry Development Association. The IC memory card contains a memory chip portion 2 which generally comprises a plurality of RAM or ROM chips (see FIG. 2). An interface connector 1 which connects the IC memory card to an external circuit is connected to each of the memory chips in the memory chip portion 2 via a lower address bus 6 and a data bus 7. The interface connector 1 is connected to a chip selecting circuit 3 designed to select a specified memory chip in the memory chip portion 2 via a control bus 4 and an upper address bus 5. The control bus 4 further extends from the chip selecting circuit 3 to each of the memory chips in the memory chip portion 2. An upper address represents an address used to select a memory chip in the RAM memory chip portion 2, and a lower address represents an address within, each of the memory chips. Actually, some of the control lines directly extend from the interface connector 1 to the memory chip portion 2, as shown in FIG. 2. An external power supply line 8 indicated by Vcc, which is the voltage of power supplied from the outside of the IC memory card through the interface connector 1, and a ground line 9, indicated by GND, also extend from the interface connector 1 to the memory chip portion 2 and to the chip select circuit 3. FIG. 2 which concretely shows the IC memory card may be a 512 K bytes RAM card memory chip portion 2 includes sixteen 256 K bytes (32 K bits.times.8 bits) SRAMs (Static Random Access Memories) 2-0 to 2-15. The chip select circuit 3 consists of, for example, a 74HC138. A card enable control line [CE]41 extends from the interface connector 1 (see FIG. 1) to the chip select circuit 3, and chip selection control lines [CS0 to CS15] 42 extend from the chip selecting circuit 3 to the individual SRAMs 2-0 to 2-15. The lower address bus 6, an output enable control line [OE]44, a write enable control line [WR] 45 and the data bus 7 respectively extend from the connector 1 to the individual SRAMs 2-0 to 2-15. An address signal which is applied to the chip select circuit 3 via the upper address bus 5 is a 4-bit signal consisting of upper address bits A15 to A18. An address signal which is applied to each of the memory chips via the lower address bus 6 consists of lower 15 address bits A0 to A14. Further, a data signal which is applied via the data bus 7 consists of 8 data D.sub.0 to D.sub.7. Since the RAM card shown in FIG. 2 contains sixteen SRAMs, and has an address length of 19 bits and a data length of 8 bits, it has a memory capacity of 512 K bytes. It is controlled in the same manner as that in which a usual RAM is controlled by the control signals on the card enable control line 41, the output enable control line 44, and the write enable control, line 45 when data is written in and read out from it, respectively.
In general, the IC memory card is connected to a computer system as a memory, as shown in FIG. 3. In FIG. 3, a computer system 10 which may be a personal computer has three 512 K byte IC memory cards, 103, 104, and 105. The IC memory cards 103, 104, and 105 are connected to a microprocessor 100 and a main memory 102 of the computer system via a system bus 101 and a connecting line 106 which includes the data bus, the address bus, and the control lines (not shown respectively) for the IC memory cards. An address decoding circuit 107 which is connected between the system bus 101 and the IC memory cards 103, 104, and 105 generates a card enable control signal for each of the IC memory cards 103 to 105 and supplies the generated signal to each of the cards via the corresponding card enable control line 41. A start address for each minimum memory area, each of the 512 K byte IC memory cards 103, 104, and 105 being a minimum memory area, is set up in the address decoding circuit 107. FIG. 4 shows a memory map made as a result of this start address setting. More specifically, memory capacity is extended for each boundary of 512 K bytes, i.e., for each IC memory card, which is treated as a unit, this unit being fixed. A RAM memory card is expensive and may have various capacities, for example, 32 K bytes, 64 K bytes, 128 k bytes, 256 K bytes, or 512 K bytes. In consequence, in FIG. 3 if the IC memory cards having 256 K bytes capacity are connected to the computer system 10 instead of the 512 K byte IC memory cards 104 and 105, setting of a start address by the conventional address decoding circuit 107 produces a memory map such as that shown in FIG. 5. Empty regions 104a and 105a are present in the memory map of the microprocessor 100, preventing the memory from being used efficiently. In other words, unless a means for changing the start address which is set in the address decoding circuit 107 for each IC memory card in accordance with the capacity of the IC memory card is provided separately, empty areas 104a and 105a occur on the memory map, preventing the memory map from being utilized effectively.
The conventional address decoding circuit provided in the computer system and the IC memory card connected thereto have the above-described relationship. Thus, if IC memory cards having various memory capacities are connected (or are provided), empty memory regions that are not used occur on the memory map of the microprocessor in the computer system, and the memory area cannot be used effectively.